1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and, in particular, to error detection and remedial measures in the context of integrated circuits transmitting and receiving multi-bit address and data information.
2. Description of Related Art
Encoders and Decoders for detection and correction of data errors have long been used in integrated circuits, particularly in Dynamic Random Access Memories (DRAMs), which may be susceptible to data storage errors. Methods of parity generation, storage, and checking have often been implemented in an attempt to discover where and when storage errors occur. Generally, parity is defined as the calculation of a number of asserted signals, or bits, in a collection of signals generally referred to as a bus. Typically, a “1” is considered the asserted state. In a characteristic application, a data byte containing 8 bits may be used as the base collection. As an example, if the data byte has the value “1100 1011” five bits contain the value of “1” and three bits contain the value of “0.” To track the parity of a data byte, an additional bit may be added to the byte to indicate the parity of the byte. In this case, if odd parity is desired, the parity bit is placed in the appropriate state to make the total number of asserted bits in the collection of bits including the data byte and the parity bit an odd number. Therefore, for the case of five asserted bits in the data byte, the parity bit is de-asserted to keep the total number of asserted bits odd. If, as another example, the data byte contains two asserted bits, the odd parity bit is asserted to make the total number of asserted bits in the combination of the data byte and the parity bit an odd number, namely three in this case. Parity may also be generated and checked as even parity. In even parity, the parity bit is asserted or de-asserted to make the total number of asserted bits in the collection of the data byte and parity bit equal to an even number.
In many conventional memory systems containing parity for the detection of storage errors, the additional parity bit is stored in memory along with the data byte requiring 9 bits of memory storage for each byte of data. With this extra storage bit, if the data byte and parity are stored with odd parity, when the read occurs a check is performed to verify that odd parity is present on the read data. If not, then an error has occurred in either storage or retrieval of the data.
Additionally, systems have been developed to check that an address, or other signals, communicated from a transmitter to a receiver are received correctly. In the case of address signals, detecting and possibly attempting to correct address errors is important to prevent data from being read or written to the wrong storage location. In these address fault detection systems error detection is desired for the transmission of signals, not storage. Therefore, there is no need to store the parity bit(s). Instead valid parity is generated at the transmission end, the parity and data signals are transmitted, and a check is performed to ensure that valid parity is still present at the receiving end. In addition, using additional bits beyond the parity bit, error correction codes can be combined with the parity bit. The error correction codes accompany the transmission of data and parity, allowing correction of certain errors at the receiving end that may occur in transmission. One approach to dealing with this problem of signal transmission errors and correction techniques is seen in U.S. Pat. No. 5,173,905 to Parkinson et al.
As the need for higher speed and bandwidth to memory increases, engineers push closer to the speed and signaling boundaries where transmission errors may occur. Signals between modern semiconductor devices may have very low voltage swings or may be configured as current mode signals. The smaller voltage swings reduce the acceptable margin of error even with more precise input signal level sensors. Also, pushing the signal transmissions to higher speeds means that a shorter time period exists when the signal is in a steady state of a high or a low when it can be sensed before the signal makes a transition to the next state. Computer graphics controllers and the graphics DRAMs used in graphics memory systems are particularly high consumers of memory bandwidth and therefore vulnerable to signal transmission errors.
As a result, there is a need for simple low cost detection of signal transmission and reception errors on high speed buses, particularly graphics buses, to allow for remedial measures to be taken. Additionally, there is a need to perform this operation without adding additional Input/Output (IO) signals to devices already under severe signal count constraints.